Speculative Precomputation on Chip Multiprocessors

Previous work on speculative precomputation (SP) on si- multaneous multithreaded (SMT) architectures has shown significant benefits. The SP techniques improve single- threaded program performance by utilizing otherwise idle thread contexts to run "helper threads", which prefetch critical data into shared caches and reduce the time the "main thread" stalls waiting for long latency outstanding loads. This technique effectively exploits the parallel thread contexts and the data cache sharing at all levels of the memory hierarchy that SMT provides. Chip multiproces- sor (CMP) architectures also feature parallel thread con- texts, but do not share caches near execution resources. In this paper, we first investigate SP on a basic CMP and show that while the existing SP techniques can provide per- formance improvements for single-threaded application on such CMP architectures, they fall short of the benefits pro- vided on SMT architectures due to the reduced degree of cache sharing. We then propose and evaluate several sim- ple enhancements to the basic CMP architecture, which can increase the speedup from using SP by an additional 10 to 12%.