NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFE to Break Great Memory Wall with 10 ns of PGM-pulse, 1010 Cycles of Endurance, and Decade Lifetime at 103 °C

E. R. Hsieh, J. K. Chang,T. Y. Tang,Y. J. Li, C. W. Liang,M. Y. Lin,S. Y. Huang,C. J. Su, J. C. Guo, S. S. Chung

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)(2022)

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摘要
A novel concept of NVDimm-FE has been proposed to replace the DRAM position in the memory hierarchy. A high-density 3D architecture of 3-bit-per-C FE 2-transistors and n-ferroelectric-capacitances (3-bit/c 2TnC FE ) array has been developed as a platform to realize this concept. Our results have shown that 3D 3-bit/c 2TnC FE array achieves 3.1V of the memory window, 62% of the program (PGM) efficiency, 10 ns of PGM-speed at 2.1MV/cm, excellent endurance up to 10 10 times for each state of 3-bits per C FE (8 states), and retention for decade-lifetime prediction of the ferroelectric-NVMs at 103 °C. With the assistance of 3D integration of many vertical C FE layers, the 2TnC FE has been proved to be an ultra-high-density candidate of the NVDimm-FE to break the GREAT memory wall and boost high-performance computing efficiency in the future.
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关键词
NVDimm-FE,memory hierarchy,3-bit-per-CFE 2-transistors,high density 3D architecture,ultra high density candidate,PGM-pulse,DRAM position,n-ferroelectric capacitances,high performance computing efficiency
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