Package Warpage of Whole Strip Evaluation with Interface Analysis in the Flip-Chip Die Bonding Process

The 5th Generation wireless systems popularity will push the package development into a high performance and high I/O density. The trend now in semiconductor manufacturing is to produce smaller and thinner packages especially FCCSP (Flip-Chip Chip Scale Package) which could meet current and future requirement of tighter bump pitch and smaller bump driven by the scaling of silicon feature size. However, the strip and die warpage can generate failure modes of the electric contacting between solder bump and solder pad. In order to solve the problem, it usually base on FEM (Finite Element Method) to design optimum package structure, material and fixture. But the uniformity and symmetry about fixture and material is difficult to simulate. In this paper, we will discuss using Shadow moire technology and IA (Interface analysis) system to analyze the interface gap between die and strip. The evaluation results can help to know the strip warpage and single package warpage of the overall strip, which site of strip or which edge of package has higher risk to cause die bond process yield loss. Furthermore, the compatibility and gap uniformity between fixture and strip will also be calculated. Combine these method, we can find the optimum structure, pattern and material for fixture design to effectively reduce the die bonding process yield loss. Furthermore, it can be the strip structure and material design guideline for next generation product. To accelerate the product development cycle, improve product quality and meet the growing needs of the 5th Generation wireless systems.