TCAD Simulation Performance of VGAA for 4F2 High Density DRAM Cell

With continuous scaling-down of the DRAM technology node, the junctionless vertical gate all around device (JL-VGAA) becomes the mainstream transistor for 4F ² DRAM cell. Simulating the JL-VGAA device using 3D-TCAD before wafer fab-out is indispensable for saving R&D cost. Here, we simulate the JL-VGAA performance based on the preliminary results of Su’s work [2]. Doping profile of JL-VGAA and diameter variation are the two key parameters affect its performance. Hence, we optimized the channel doping, after data normalization, the I on is simulated as 17.6, and the I off is 1.2×10 ^-12 . The ratio of I on and I off is approximately 1.4×10 ¹³ . In addition, the variation of V th is around 10 mV nm ^-1 with low-level channel doping, which is excellent among other devices. Finally, the word line (WL) and bit line (BL) coupling capacitance were calculated. Overall, the total capacitance of JL-VGAA is less than the state of the art of emerging DRAM structure. Future research should further develop and confirm these initial findings by this paper.