Package Design and Measurements for Radar Emulator using Accelerators and Photonics

Real-time radar emulators require high-speed computing operations where large amounts of data need to be stored and processed. This requires a high-speed computer architecture consisting of multiple CPU nodes networked to each other through optical fibers, to ensure that each node can communicate with every other node. Each CPU node consists of an accelerator IC (ACC) for matrix multiplications and multiple photonic ICs (PIC) for data transmission. The focus of this paper is on the electrical characterization of interconnects in an organic package that establishes communication between the ACC and PIC at a speed of 16 Gbps. Custom integration of photonics with electronics in a single module is required for supporting the required bandwidth, speed, and energy efficiency. In this paper, we explore several variations of the interconnect technology placing emphasis on the importance of impedance matching between the electronic drivers and the photonic modulators. To enable the implementation of these interconnects we have designed a test vehicle (TV) with varying topologies for electrical characterization up to 110 GHz. In addition to the design, this paper presents the characterization of interconnects in the fabricated TV, of varying impedances, lengths, and spacing on multilayer organic substrates with very low loss-high frequency dielectric materials. The losses are characterized up to 110 GHz for microstrip lines, striplines, vias, microstrip, and ring resonators, along with a full channel characterization with an impedance range of 50 similar to 80 Ohm and short interconnect lengths in the range 1 similar to 5 mm, respectively. This paper includes model to hardware correlation studies.