Cryogenic Ultra-Fast Bias Temperature Instability Trap Profiling of SiC MOSFETs

4H-SiC transistors suffer from bias temperature instabilities (BTI) due to traps at, or near, the SiO 2 /SiC interface. These traps result in low inversion layer mobility of SiC MOSFETs as well as an observed hysteresis of the I d V g transfer characteristic. They are distributed in energy (within the SiO 2 bandgap) and location (e.g. interface and border traps). The most challenging traps to assess are those close to the SiC conduction and valence bands, whose time constants can be below the μs-regime at room temperature. These ultra-fast traps have a strong impact on the transistors' functioning and lead for instance to apparent negative temperature activation of threshold voltage drift. Although these traps are too fast for direct experimental assessment at room temperature, we will demonstrate that they can be closely studied at cryogenic temperatures due to their strong temperature-dependent activation. This work provides experimental ultra-fast BTI (uf-BTI) data from 80K up to 300K to monitor the ultra-fast shifts of the threshold voltage, in addition to theoretical trap-profiling which allows for a precise extraction of (a) the energic distribution and (b) the trap location within the SiO 2 dielectric.