Nondestructive Electrical Characterization Of Integrated Interconnect Line-To-Line Spacing For Advanced Semiconductor Chips

Poor process controls may cause huge line spacing variation across a semiconductor wafer during back-end-of-the-line integration in advanced semiconductor integrated circuit fabrication. As a consequence, significant degradation in yield, performance, and reliability may be observed. Line spacing variation also imposes challenges for accurate time dependent dielectric breakdown reliability lifetime projection. In this paper, a nondestructive, fast electrical method for determining a line-to-line spacing of a semiconductor chip is proposed. The method includes experimentally determining a slope from capacitance measurement (k(CA)), experimentally determining a slope from current-voltage measurement (k(SE)), and finally determining a line-to-line spacing from the slope k(CA) and the slope k(SE). The line-to-line spacing determined from this method shows an excellent agreement with constructional analysis data.