Applicability of dual layer metal nanocrystal flash memory for NAND 2 or 3-bit/cell operation: Understanding the anomalous breakdown and optimization of P/E conditions

P K Singh,C Sandhya,Kshitij Auluck,Gaurav Bisht,M Sivatheja,Gautam Mukhopadhyay,S K Mahapatra,Ralf Hofmann

Reliability Physics Symposium（2010）

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摘要

Large memory window (6-9V) program/erase (P/E) cycling endurance is studied for evaluating their suitability for MLC operation. Effect of NC area coverage and device size is evaluated using statistical method. Constant voltage stress (CVS) measurements and 2-D simulations are extensively used to evaluate the impact of carrier; type, fluence, and energy on the defect generation process in the gate stack. Degradation during P and E are isolated to allow individual optimization for improving the cycling reliability. P/E cycling endurance >104 at 8V MW and >2.5×103 at 9V MW are shown for first time in metal NC memory devices using the proposed distributed cycling scheme.

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关键词

circuit optimisation,circuit reliability,flash memories,logic gates,nanostructured materials,statistical analysis,2-d simulations,cvs measurements,mlc operation,nand 2-bit/cell operation,nand 3-bit/cell operation,nc area coverage,p/e conditions optimization,anomalous breakdown,constant voltage stress,cycling reliability,defect generation process,device size,distributed cycling scheme,dual layer metal nanocrystal flash memory,gate stack,memory window,metal nc memory device,program/erase cycling endurance,statistical method,voltage 6 v to 9 v,flash memory,mlc,metal nanocrystal,component,reliability,nc,metals,voltage,performance,nonvolatile,stress,nanocrystals,annealing

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