Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.

Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense research and development investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012), and could be used as both computing and storage memories beyond flash memories. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure enough current for the switching operation. This paper presents the design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells with a particular focus on reliability and power performance investigation. This architecture allows fewer selection transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture and provide fast data access for computing purpose. We perform transient and statistical simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 40 nm design kit and memory compact models, which were developed based on relative physics and experimental parameters.