Power and Energy Impact by Loop Transformations

Power dissipation issues are becoming one of the major design issues in high performance processor architectures. In this paper, we study the contribution of com- piler optimizations to energy reduction. In particu- lar, we are interested in the impact of loop optimiza- tions in terms of performance and power tradeoffs. Both low-level loop optimizations at code generation (back-end) phase, such as loop unrolling and soft- ware pipelining, and high-level loop optimizations at program analysis and transformation phase ( front- end), such as loop permutation and tiling, are stud- ied. In this study, we use the Delaware Power-Aware Compilation Testbed (Del-PACT) — an integrated framework consisting of a modern industry-strength compiler infrastructure and a state-of-the-art micro- architecture-level power analysis platform. Using Del-PACT, the performance/power tradeoffs of loop optimizations can be studied quantitatively. We have studied such impact on several benchmarks under Del-PACT.