Interface failure behavior and mechanisms of 4H-SiC wafer with alloy backside layer caused by different dicing technologies

Vertical 4H-SiC power devices tend to be dominant in the field of power devices because of their easy realization of miniaturization and excellent high-temperature, high-frequency, and high-voltage performance. Typically, the wafer for vertical 4H-SiC power devices have high-hardness of 4H-SiC, containing alloy backside layer, and large-thickness wafer characteristics. Considering the unreasonable dicing process will cause the interface failure and affect properties, two combined dicing technology (laser ablation and stealth combined dicing, microgrinding and stealth combined dicing) are proposed to compared with single stealth dicing from microstructure of the epitaxial layer, sidewall, and the microgroove on the alloy backside layer, and focus on study the peeling failure at 4H-SiC and alloy backside layer interface. Single stealth dicing technology cannot coordinate the material characteristics of multilayer, thereby leading to the torn of the alloy interlayer. Laser ablation and stealth combined dicing can solve the torn of the alloy interlayer problem by laser ablation. However, peeling failure at alloy backside layer and 4H-SiC interface is produced due to thermal stress. By virtue of the compatibility, precise control, and low strain of microgrinding and stealth combined dicing, no delamination occurs in the epitaxial layer, and there are no separation and peeling gap between alloy backside layer and 4H-SiC. This paper provides an avenue for the high-quality dicing of 4H-SiC wafer with alloy backside layer.