Control of Surface Chemistry in Recess Etching toward Normally Off GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors

Reducing off-state and gate leakage current is crucial in the development of metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). This work reports interface engineering in the gate recess region through low-damage digital etching during the fabrication of normally off GaN MIS-HEMTs. Conventional plasma etching leads to a reduction of the N/(Al+Ga) ratio, but this value recovers to almost 1 with optimized oxidation condition during digital etching, suggesting a reduction of the Al/Ga dangling bonds based on the proposed technique. GaN MIS-HEMTs with digital etching exhibits a threshold voltage of 1.0 V at 1 mu A mm-1, a high ON/OFF current ratio of 1010, a gate breakdown voltage of 22 V, and a low gate leakage current of 10-8 mA mm-1. Normally-off GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) was fabricated. With optimized oxidation power, N/(Al+Ga) ratio in the gate recess region recovers to 0.96, identical to that of the pristine HEMT surface, suggesting a reduced number of Al/Ga dangling bonds and lower surface defects. The proposed device exhibits low leakage current and high on/off ratio.image (c) 2024 WILEY-VCH GmbH