Impact of Operational Parameters on dVDS/dt of SiC MOSFET and a Scheme for Gate Driver Resistance Selection to Limit dVDS/dt

SiC MOSFETs enable fast switching that results in the development of a high dV DS /dt across the device. High dV DS /dt is reported to accelerate the degradation of various components and cause reliability issues in many power electronics applications. Further, the value of dV DS /dt is affected by various parameters that change during the operation of a power converter. Hence gate driver resistance selection process to limit dV DS /dt to a desired value, must include the impact of all the operating parameters in the selection process. However, such a methodology incorporating the impact of all key parameters i.e. (i) device current (I DS ), (ii) junction temperature (T J ), and (iii) drain to source (V DS ) blocking voltage, has not been reported in the literature. This manuscript first presents an analysis on the impact of these three parameters on dV DS /dt. Furthermore, this manuscript considers devices from different manufacturers and investigates the variation in their impact on dV DS /dt due to operational parameter variation. Next, it presents a scheme for gate driver resistance selection based on the aforementioned analysis. Finally, experimental results are included (i) to validate the analysis, (ii) to show the device-dependent variation in the impact on dV DS /dt, and (iii) to validate the proposed gate resistance selection scheme.