Multi-Stage Speculative PAM4 Decision Feedback Equalizer for Short Reach Applications

The drive for higher per-lane data rates has led to increased complexity in wireline transceiver architectures due to the need for higher-order equalization. This has the potential to result in degraded energy and area efficiency of these transceivers. A new multi-stage decision feedback equalizer (DFE) design approach that leverages speculative intersymbol interference (ISI) cancellation to achieve low complexity is proposed. A 2-tap multi-stage PAM4 DFE design example that uses lower than 35 $\%$ of the components of a conventional speculative DFE, and can be applied to most channel profiles, is used to discuss the equalization capability of the proposed approach. It is also used to discuss the impact of circuit nonidealities on performance. Simulation results of the multi-stage DFE over three different channels showed matched equalization performance to the conventional designs, even as it promises higher data rates than the direct feedback DFE and drastically higher energy efficiency than the conventional speculative DFE.