A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process

An input/output (110) buffer is developed to meet the specifications for DDR4 and DDR5 SDRAMs in terms of duty cycle, system voltage, and slew rate. As a means of reducing output current variations and increasing driving current, ultra-low threshold voltage (ULVT) transistors are opted for as output stage's driving devices. The gates of these transistors are stabilized thanks to the work of the novel VDDIO Detector circuit and an on-chip MIM capacitor that cancels out noise coupled from GND. Leakage currents are minimized by the modified Leakage Reduction and Floating N-well circuits. TSMC's 16-nm FinFET CMOS technology was used to realize the 1/0 buffer. The core area is $0.242\times 0.126 \ \text{mm}^{2}$ . It has operated reliably at a maximum worst case frequency of 2.6 GHz. At 2.2 GHz, $i$ t achieves a slew rate of 8.89 V/ns (0.8 V VDDIO) and 8.85 V/ns (1.2 V VDDIO), as well as a duty cycle of 48.0% (0.8 V VDDIO) to 48.2%. (1.2 V VDDIO). After auto-tuning the driving current, the slew rate (SR improvement) is increased by at least 28 % at high voltage mode (VDDIO).