Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application

Ultra-dynamic voltage scaling (UDVS) is a popular trade-off technique between delay and power performance. However, voltage scaling will degrade the radiation-aware reliability of traditional latch obviously. In addition, although the shrinkage of feature sizes results in the reduction of latch area, the occurrence possibility of double node upset (DNU) and triple node upset (TNU) events are increasing. Achieving a good balance among delay, power, area and reliability performance is becoming an important issue in the design of radiation-hardened latches, especially considering the coming commercial aerospace applications. Therefore, this paper proposes a TNU self-recoverable latch with wide voltage range (TRLW), which is low overhead and very suitable for UDVS technique. The TRLW latch is mainly composed of two completely interlocking triangle structures, and is able to self-recover from any possible TNU event. Clock-gated isolated cells are skillfully utilized to avoid current conflict. Meanwhile, six transmission gates are carefully integrated into TRLW latch to reduce the propagation delay t(d2q) and critical path delay t(crit). Accordingly, the overall performance of TRLW latch is always excellent from normal voltage to near-threshold voltage (NTV). Simulation results based on 28nm CMOS process show that TRLW latch can achieve complete SNU, DNU and TNU self-recovery in all possible cases, and the soft error rate of TRLW latch only raises by 4.6 % when the supply voltage is decreased from 0.9 V to 0.3 V. Moreover, compared with the other reported TNU self-recovery latches, TRLW latch consistently achieves the minimum delay, power, area and delay-power-area product (DPAP) under different process, voltage and temperature (PVT) conditions, and obtains average reductions of 3.43 x , 3.03 x , 2.66 x , 1.40 x and 10.83 x for t(d2q), t(crit), power, area and DPAP when operating from 0.5 V to 1.0 V.