Design of high-precision time measurement prototype ASIC for the LGAD readout

A low gain avalanche detector (LGAD) represents a type of semiconductor detector with the advantages of high time precision and spatial granularity, and it has been widely studied worldwide. Considering the number of channels and density in the LGAD implementation process, array-structure application-specific integrated circuits (ASICs) with a high-precision time measurement ability are required for the LGAD readout. In this study, a prototype ASIC named the LATIC1 for LGAD readout is proposed based on 130 nm CMOS technology. The proposed LATIC1 is a 5 × 5 array ASIC structure that consists of analog front-end circuits and integrated time-to-digital converters (TDCs). This type of ASIC structure is required to achieve a time precision of better than 25 ps for the input LGAD signal with an amplitude as small as 10 fC. To achieve this goal, a pre-amplifier structure using the trans-conductance of both PMOS and NMOS is adopted for achieving a higher signal-to-noise ratio (SNR). The amplified signals are discriminated into digital pulses and measured by the on-chip TDCs integrated into each channel. In addition, the on-chip design for test (DFT) circuits are integrated and used for ASIC calibration and performance evaluation for each channel. The test results indicate that a time precision of better than 25 ps, including the analog front-end and TDC circuits, can be successfully achieved with a 10-fC input charge and a 4-pF capacitance, which meets the application requirements.