Structure and RF performance evolution of polycrystalline silicon charge capture layer for advanced RF-SOI in in-situ annealing process

In this paper, the structures and radio-frequency (RF) properties of high resistivity silicon (HR-Si) wafers with a polycrystalline silicon (Poly-Si) charge capture layer after in-situ annealing were investigated. The thermal treatment significantly improves the wafer warpage and optimize the resistivity of Poly-Si/HR-Si interfaces. By using spreading resistance profiling (SRP), energy dispersive spectrometer (EDS) and secondary ion mass spectrometry (SIMS) technology, the rise of interfacial resistivity may be as results of the pyrolysis of the native oxide and the diffusion of hydrogen atoms. The transmission Kikuchi diffraction (TKD) analysis exhibited that the grains were recrystallized during the annealing, leading to the transformation from the small angle boundaries (SAGBs) into low-Σ coincidence lattice grain boundaries (CSL GBs). The drop of the bulk resistivity of the Poly-Si layer is attributed to the reduction of the total grain boundary (GB) density and the increase of the low electro-activity GB density. Moreover, the microwave losses and non-linearity of the RF-SOI with embedded Poly-Si layer was evaluated by on-chip testing based on CPW. It was determined that the decrease in the Poly-Si resistivity only worsens the microwave losses but not the non-linearity.