22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration

High-speed $(\gt{\mathrm GS/s})$ medium-resolution (6-8b) ADCs are in high demand for wideband applications. The time-interleaved (TI) SAR ADC is widely used for its superior power efficiency. However, TI ADCs suffer from timing-skew mismatches that severely limit the performance. Some background timing-skew calibration methods rely on input derivative or input statistics such as autocorrelation [1] to detect timing-skew errors. These methods place limitations on the input signal, e.g., must be at high frequency, with large amplitude, have frequent zero crossings, etc. To be applicable to all types of input signals, some prior works inject a reference clock signal to sense the timing-skew errors [2–3]. Reference [2] injects the reference clock with slow rising edges to each interleaved channel. The timing-skew errors are detected by the difference of the injected voltages among channels. Nonetheless, it suffers from mismatches among different dither injection paths, leading to large residual timing-skew errors after calibration. Reference [3] injects the reference clock in the input common mode. However, common-mode voltage variations, as well as switch and routing mismatches among channels still result in large residual timing-skew errors. Furthermore, the periodic sampling in the calibration engine causes input impedance variation and generates spurs in the output spectrum [3]. To eliminate the residual errors and spurs, while maintaining applicability to all types of input signals, this work proposes a new background timing-skew calibration method that injects a dithered reference clock at the input buffer.