15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10 12 Write Endurance and Integrated Margin-Expansion Schemes.

Ku-Feng Lin, Hiroki Noguchi,Yi-Chun Shih, Perng-Fei Yuh,Yuan-Jen Lee,Tung-Cheng Chang,Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng,Yu-Jen Wang,Harry Chuang,Yu-Der Chih,Yih Wang,Tsung-Yung Jonathan Chang

IEEE International Solid-State Circuits Conference(2024)

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摘要
STT-MRAM has been demonstrated as a viable embedded non-volatile memory (NVM) with 20-year data retention at 150°C, a high write endurance (>1M cycles), and the ability to tolerate solder reflow [1]. However, for working memory applications, even higher endurance, fast write speed, and small memory size are necessary. By optimizing the magnetic-tunnel-junction (MTJ) stack for a lower write current, while relaxing retention requirements (e.g., 1 min @ 125°C), STT-MRAM can achieve a higher endurance (>10 12 cycles) and a smaller bit cell size. Therefore, STT-MRAM is a promising alternative to SRAM as a working memory solution, while also offering a higher memory density compared to SRAM-based solutions.
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关键词
Cell Size,Density Data,Current Reference,Parasitic Capacitance,Small Cell Sizes,Non-volatile Memory,Data Retention,Read Operation,High Endurance,Large Step Size,Trimming Step,Near-side
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