Pipelined training accelerator for portable devices

To perform classification for a particular application, a Decision Tree (DT) model first needs to be trained using that application data. Due to high complexity, DT training implemented on software platforms is timeconsuming. So, hardware platforms like Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASICs) can be used to accelerate the process. Also, DT training hardware can be used for a different application simply by altering the training data. The hardware cost can be reduced by optimizing and reducing the training complexity. Thus, this paper proposes a pipelined architecture for low complexity Hybrid Decision Tree (HDT) algorithm. The maximum operating frequency of the proposed hardware is found to be 200 MHz on FPGA. Simulation results show that FPGA-based implementation is at least 56x faster than the C -based realization. ASIC implementation of the design occupies a total area of 0.744 mm2 @200 MHz as synthesized on UMC 65 nm technology node and hence suitable for portable devices.