Automated Design Flow for Synthesizable ADPLL: From Specification to GDS

We propose an automated design flow for an all-digital phase-locked loop (ADPLL) that selects and implements a PLL layout that satisfies user given input specifications using place-and-route (PnR) tools within 1.2 hours. The all-digital architecture enables the use of a theory-based frequency domain model for predicting the output specifications once the oscillator performance is characterized. The cell-based digitally controlled oscillator (DCO) is modeled by extracting the PDK and cell specific constants that characterize the effective current to capacitance ratio from only 3 sets of SPICE simulations. The constants are then used to predict the analog performance with an analytical model, which shows an error rate less than 1.5% for estimating frequency range and power consumption. The generator guides the user to a feasible set of specifications using the analytical model by providing the achievable range of the failed specification. As design examples, 8 generated PLL designs and their post-parasitic performances are compared to input specifications, including one measurement result from a fabricated chip in 65nm CMOS process.