Adaptive Time-Triggered Network-on-Chip Architecture: Enhancing Safety

Real-time computing systems are designed to meet strict timing constraints and respond to events or inputs within specific deadlines. These systems are commonly used in safety-critical applications such as spacecraft, medical devices, industrial control, and automotive systems. Engineers rely on various scheduling techniques to ensure that timing constraints are met. One such technique is static allocation in time-triggered systems. This technique offers valuable advantages in terms of system safety and dependability. It enables efficient resource usage in Network-on-Chip (NoC) architectures by minimizing message congestion and contention. However, its static nature can present limitations in terms of fault tolerance. This paper focuses on developing and evaluating fault tolerance techniques tailored for NoC-based multi-core architectures to enhance safety. It introduces adaptation techniques that tolerate permanent faults within the time-triggered NoC architecture. Additionally, the paper outlines the incorporation of seamless redundancy mechanisms at the network interface (NI) level, specifically designed to tolerate transient faults that may occur within NoC components, such as routers and links. These mechanisms play a crucial role in safeguarding critical data, further enhancing the reliability and safety of real-time systems in safety-critical applications.