NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node

Over the past decade, numerous compute-in-memory (CIM) platforms have been proposed in the literature.While emerging non-volatile memory based analog CIM (ACIM)has been widely studied, its silicon demonstrations are in themature legacy node (22 nm or above). As an alternative, digitalCIM (DCIM) based on static random access memory (SRAM)is recently drawing significant attention, as it enjoys the scalingbenefits with the logic process to the leading-edge node (5 nmor below), and does not suffer from the accuracy loss dueto process/voltage/temperature (PVT) variations. To assess thepotential of DCIM in the future, we release NeuroSim V1.4,a CIM benchmark framework, which supports advanced tech-nology nodes down to 1 nm node. We project the technologyparameters (standard cell, transistor and interconnect) usingTCAD device simulations, interconnect modeling, and the avail-able industry/IRDS roadmaps. State-of-the-art technology trendssuch as fin-depopulation, buried power rail, stacked nanosheet,etc are captured in the updated parameters. Technology scal-ing down to 1 nm enables DCIM to achieve 1.4 similar to 1.8xand44.1 similar to 63.1xhigher system-level figure of merit than state-of-the-art 7 nm SRAM-based ACIM and 22 nm RRAM-based ACIM,respectively, for representative workloads such as ResNet18 andResNet34 inference.