A novel 10T SRAM bit-cell with high static noise margin and low power consumption for binary In-Memory Computing.

In this paper, a novel 10T SRAM bit-cell with a high read/write static noise margin and low power dissipation is presented to be utilized in binary in-memory computing. The proposed SRAM bit-cell employs a conventional 6T SRAM along with four extra transistors to decouple read and write operation paths and improve the stability of the bit-cell. The two transistors M7 and M8 in the proposed structure act as switches to enable binary operation of the dot product in IMC mode. To conduct a comparative analysis, the various SRAM bit-cell designs were simulated using the Cadence design framework in the 65 nm technology. The proposed SRAM bit-cell not only presents a higher read stability value among the considered cells but also has a proper read delay value. The read noise margin of the proposed circuit is 1.91× as compared to a conventional 6T SRAM bit cell. Furthermore, the read energy of the proposed 10T SRAM has the lowest value of 28 fJ at a supply voltage of 1V compared to all the considered SRAM bit cells.