An Efficient DSP Simulator Design Supporting Multi-Core Debugging.

In order to accommodate the ancillary development of compilers and other toolchains in the multi-core digital signal processors (DSP), simulator debugging systems are indispensable. This paper proposes a multi-core simulator debugging architecture, comprising the implementation of multi-core debugging proxy and multi-core simulator. To enhance the runtime performance, this paper changes the processing of FILEIO from the GDB endpoint to the proxy endpoint. It also appends a pre-decoder module to the simu-lator and optimizes the decoding strategy by substituting the previous hash matching method with a decision forest method to accelerate FILEIO operations. And this system has good scalability for Harvard structured DSP, requiring only modi-fication of instruction set and register definitions, and has good support for adding peripherals. Ultimately, by comparing various types of test cases, the functionality and performance of the system are validated, and the running speed is greatly improved with the proposed optimization.