Gain Cell Memory on Logic Platform – Device Guidelines for Oxide Semiconductor Transistor Materials Development
2023 International Electron Devices Meeting (IEDM)(2023)
摘要
This work starts with memory macro simulation and establishes guidelines for oxide semiconductor (OS) transistor co-designed for gain cell memory on the logic platform. ALD Indium Tin Oxide FET is chosen to balance retention time with memory bandwidth. The experimentally optimized device has low off-current 2×10
-18
A/μm, high on-current 26.8 μA/μm, and low V
TH
shift <0.2 V under 125°C, low PBS shift <0.35 V and low NBS shift <0.1 V under 1000s bias stress. OS / hybrid gain cell memory macro with 64 row (WL) × 256 col. (BL) simulated at 28nm node using this optimized device operates at V
DD
= 0.9 V, has 480, 000× retention, 1.5× / 4.1× frequency compared with Si gain cell, and 0.5× / 0.98× frequency of SRAM. Hybrid OS-Si gain cell has 3× density of SRAM, and OS-OS gain cell has N times 1.15× density of SRAM with N-layer of 3D stacking. DNN simulation shows ~50% reduction in execution time due to larger on-chip memory capacity.
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关键词
Oxide Semiconductor,Oxide Semiconductor Transistors,Logic Platform,Chromatography,Reduction In Time,Indium Tin Oxide,Memory Bandwidth,On-chip Memory,Reduction In Execution Time,Bias Stress,Higher Density,Carrier Mobility,Gate Dielectric,Path Delay,Memory Array,Memory Wall
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