A 64Gbps 1.36 Vppd 1.44pJ/b Fully CMOS-Style Transmitter with Active Hybrid Driver in 28nm CMOS

The next generation wired communication interfaces for 400Gbps electrical links must meet higher standards for power consumption, area, and signal swing amplitude in addition to the needed speed improvement. To solve these issues, this paper presents a 64Gbps fully CMOS-style transmitter (TX) in 28nm CMOS. The transmitter incorporates a fully active hybrid voltage-current mode driver with three-tap feed-forward equalization (FFE) to increase differential output swing. The TX serializers, equalizer, and driver use a fully active CMOS-style topology to increase bandwidth while minimizing area. A new active hybrid voltage-current mode and swing enhancement technology are implemented in the FFE and Driver combining IDAC. Implementing an equalization (EQ) scheme is straightforward and flexible. The post-layout simulation results indicate that the running rate can be as high as 64Gbps while consuming only 92.4mW of power and as low as 1.44pJ/b for power efficiency. Peak-to-peak differential output swing (V ppd ) at 1V supply voltage can reach 1.36V. The layout of the TX front-end core circuit is 0.027 mm2.