ASIC and FPGA Implementation of Radix-2² 32-point MDC-FFT Architecture

This paper presents a high-speed radix-2 ² 32-point multi-path delay commutator (MDC) Fast Fourier Transform (FFT) architecture. The architecture has been successfully synthesized and implemented in Virtex-7 FPGA using Xilinx-Vivado and UMC 65nm technology Synopsys tool. The pipelined architecture has simple butterfly units with reduced number of rotators and a re-shuffling circuit for proper sequencing of data entering into the butterfly of the next stage from each of the preceeding stages. The optimization of computation intensive blocks offers significant reduction of area, delay and power consumption to be advantageous in the field of high-speed digital signal processing. The FPGA results show area, delay and power consumption of 3906 LUTs, 3.830 ns and 333 mW respectively while ASIC results show area, delay and power consumption of 0.049 nm ² , 3.85 ns and 2.167 mW respectively.