A Compact Front-End Circuit for a Monolithic Sensor in a 65 nm CMOS Imaging Technology

This work presents the design of a front-end circuit optimized for a monolithic active pixel sensor with a small, low-capacitance collection electrode. This work was carried out in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade in a first exploration of the TowerJazz Panasonic Semiconductor (TPSCo) 65 nm imaging technology. The circuit was integrated into a 1.5 mm × 1.5 mm proof-of-principle prototype, the Digital Pixel Test Structure or DPTS, featuring a sensitive area of 32 × 32 pixels with a 15 μm pitch. The front-end occupies an area of ~ 42 μm ² and, together with the digital readout, allowed this small pitch. The sensor was optimized to reduce charge sharing and concentrate charge on the seed pixel as much as possible to increase operating margin. This very first prototype proved fully efficient in test beam, validating not only the front-end but also the sensor and the digital readout circuitry. First measurement results on the front-end will also be shown.