A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications.

Tunnel Field Effect Transistor (TFET) which has a subthreshold swing lower than 60mV/decade and ultra-low off-current has become one of the most promising candidates to replace MOSFET in ultra-low-power applications, such as artificial intelligence of things. In this paper, we study the TFET-based static random access memory (SRAM) design and propose a novel 8T TFET-MOSFET hybrid SRAM based on the compact model of recently manufactured TFET in 12-inch foundry platform. The proposed design uses a single MOSFET as the write access transistor and the TFET-MOSFET stacked structure as the read access transistor which eliminates the forward p-i-n current fundamentally. Compared with 6T CMOS SRAM, the proposed design demonstrates 3 orders of magnitude lower static and read power, and 6 orders lower write power. Besides, it achieves faster read and write speed than other reported TFET SRAM designs. It also has the maximum hold, read and write static noise margin among all the CMOS and TFET SRAM designs.