Gate Driver Design for SiC Power MOSFETs with a Low-Voltage GaN HEMT for Switching Loss Reduction and Gate Protection

The design of gate drivers for SiC power MOSFETs needs to address various adverse effects induced by the parasitic inductance in the gate loop, such as false turn-on, gate overstress, and reduced switching speed. In this work, a single-polarity gate driver design featuring a low-voltage (LV) GaN HEMT for Miller clamping is presented. The lateral LV GaN HEMT can switch at a much higher speed than that of the SiC MOSFET, so that the proposed gate driver can well suppress false turn-on with a user-friendly OFF-state gate voltage of 0 V. Meanwhile, the reverse-conduction characteristics of the LV GaN HEMT allow the clamping of negative voltage spikes to protect the SiC MOSFET against gate overstress, which is shown to be detrimental to the gate reliability. In addition, the LV GaN HEMT can accelerate the turn-off process and suppress the gate-loop oscillation, thereby further reducing the switching loss, as verified by experiment results.