Boost in Carrier Velocity Due to Electrostatic Effects of Negative Capacitance Gate Stack

We show that a boost in injection velocity results from increased dielectric confinement of electric fields in low EOT (Effective Oxide Thickness) gate stacks. This is demonstrated by extracting injection velocity from experimental measurements of 90 nm channel length Negative Capacitance MOSFETs that utilize a1.8 nm ferroelectric-antiferroelectric (FE-AFE) HfO2-ZrO2(HZH) superlattice gate stack. The velocity enhancement becomes more pronounced at low temperatures where carrier screening and phonon scattering effects are diminished. An analytical velocity model based on carrier scattering explains the experimental data. The model further predicts substantial improvement in velocity and operating voltage at room temperature as EOT is scaled down from 9.5 & Aring; to 6.5 & Aring;.