Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider Controllers.

Fractional$- N$ digital phase locked loops (DPLL’s) typically use a digital-to-time converter (DTC) to cancel the quantization error (QE) produced by the divider controller that is typically a digital $\Delta- \Sigma$ modulator (DDSM). In practice, the nonlinear transfer characteristic of the DTC interacting with the accumulated QE of a conventional Multi-stAge noiSe-sHaping (MASH) DDSM causes fractional spurs which deteriorate the system’s output phase noise performance. The Enhanced Nonlinearity-induced nOise Performance (ENOP) DDSM exhibits fractional-spur immunity when interacting with nonlinearities that can be modeled by polynomial functions. This paper compares the generation of fractional spurs when using MASH and ENOP DDSMs respectively. The application of the latter in a DPLL is shown to successfully mitigate the fractional spurs. Block and system level behavioral simulations underpin our observations.