FPGA implementation of compact and low-power multiplierless architectures for DWT and IDWT

Wavelet transform is an important tool in the field of multimedia signal processing. Due to the growing demand for hardware-based design in the field of image, video, and speech signal processing, several researchers have implemented different discrete wavelet transform (DWT) architectures and measured their performances. In this paper, FPGA implementation of compact and low-power VLSI architectures for one-dimensional and two-dimensional DWT and inverse discrete wavelet transform (IDWT) based on lifting and lattice schemes have been proposed. The adder–subtractor-based design approach has been used to replace the multiplier without affecting the precision. Hardware and timing analysis of existing and proposed 1D and 2D architectures are presented here. The proposed and existing DWT and IDWT architectures are also simulated and synthesized in a Virtex-4 FPGA device. The number of slice LUTs, slice registers, clock frequency, delay, power, and power-LUTs product (PLP) of proposed DWT and IDWT architectures based on lifting and lattice schemes have been found using Xilinx Vivado synthesis tool. The proposed design is also implemented on Basys 3 Artix-7 FPGA board and synthesis results show a significant improvement in terms of area and power compared to other existing architectures.