Experiments of a Novel Low-Voltage LDMOS With Ultrashallow Low-Resistance Path Modulated by Bulk Superjunction

A novel low-voltage LDMOS with ultrashallow low-resistance path (ULP) modulated by the bulk super-junction (SJ) is proposed and experimentally demonstrated in this article. The new device features a highly doped surface ULP structure that acts as a low-resistance current path directly connecting the source and drain in the ON-state and is fully depleted by a step tungsten plug field plate (TP-FP) in the OFF-state. A charge-balanced SJ is further introduced in the bulk of the ULP LDMOS to modulate the bulk field, thereby improving the safe operating area (SOA). Experimental results have demonstrated that the ULP LDMOS has achieved a ULP with an injection depth of 100 nm and a short channel length of 150 nm, with a measured specific ON-resistance R-ON,R- sp of only 7.07 m Omega center dot mm(2) under a breakdown voltage V-B of 41 V. This represents a reduction of 21.1% compared with the "silicon limit." In addition, the TP-FP reduces the gate charge Qg by 43.5% when compared with that of the conventional devices, achieving the best reported FOM = R-ON,R- sp center dot Q(g) characteristics.