A High-Precision Delay Faults Testing Technique Based on the Improved DWR Structure

Aiming at the challenge of testing delay faults in through silicon via (TSV) of Chiplets, a high-precision delay faults testing technique based on the improved die wrapper register (DWR) is proposed. Relying on time-to-digital converter (TDC) embedded in the original DWR, transitional signal is propagated in delay chains and conversed into a digital signal to observe whether there is the delay fault. The double delay chains are constructed by two kinds of XOR gates with different delays. The conversion with high precision is achieved by dividing the transition signal into continuous small time-intervals. With the improved test access port controller (TAPC) circuit, the time to configure effective test path is greatly reduced and the delay test can be realized without additional external interfaces. The simulation results demonstrate that delay faults can be detected within the precision of 11.246ps and the time of test configuration is reduced.