Silicon-van der Waals heterointegration for CMOS-compatible logic-in-memory design

Silicon CMOS-based computing-in-memory encounters design and power challenges, especially in logic- inmemory scenarios requiring nonvolatility and reconfigurability. Here, we report a universal design for nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By leveraging the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85 degrees C), and near-ideal subthreshold swing (80 mV dec(-1)) can be done. A comprehensive investigation of dynamic charge fluctuations provides a holistic understanding of the origins of nonvolatile reconfigurability (a trap level of 1013 cm(-2) eV(-1)). Furthermore, we cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as high-gain (65 at V-dd = 0.5 V) logic gates. This work provides an innovative 3D heterointegration prototype for future computing-in-memory hardware.