A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS.

Since the bandwidth and clock frequency of a memory interface have been increased for 5G communication, its power consumption should be tightly managed to extend battery time. To improve the energy efficiency, the dynamic voltage and frequency scaling (DVFS) technique [1] that optimally adjusts the operating voltage and frequency depending on the system scenarios has been used so that a wide frequency range of the system clock is required. For example, the advanced double data rate 5 (DDR5) mandates a clock frequency range from 2.1 to 9.6 GHz. Therefore, ring oscillator (RO) based PLLs are commonly utilized in memory interfaces due to their wider frequency tuning range when compared to LC-based PLLs. In an RO-based PLL, the output frequency can be tuned by controlling transconductance (gm) of delay cells. Typically, the current of RO adjusts gm through a current-DAC (I-DAC) with a foreground automatic frequency calibration (AFC) [2], [3]. However, as the output frequency of RO varies with respect to the process, voltage, and temperature (PVT) variations, the dynamic range of the I-DAC should cover not only the target frequency range, but also the frequency deviation over PVT variations, hence requiring large area of the I-DAC. This paper presents an RO-based PLL which uses a current reference that compensates for the frequency deviation of the RO over PVT variations; thus, the proposed PLL supports a wide frequency range from 0.019 GHz to 10.6 GHz, while occupying a small active area of 0.012mm2. The proposed PLL achieves $0.32-\text{ps}_{\text{rms}}$ period jitter and 0.53-mW/GHz energy efficiency at 10.6-GHz output frequency.