A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.

This brief presents a 4-GS/s 6-bit single-channel time-to-digital converter (TDC)-assisted analog-to-digital converter (ADC). The proposed hybrid-domain pipeline ADC adopted flash and unipolar TDC as the $1^{st}$ and $2^{nd}$ quantizers. By normalizing the discharge current source between the cascode-current based voltage-to-time converter (VTC) and fully-differential delay cell, the overall ADC is insensitive to the power supply variation. Together with a no-resistance current reference generator, the inter-stage gain error (IGE) caused by the process, voltage and temperature (PVT) variation can be eliminated. A prototype chip has been implemented using the proposed architecture in 28-nm CMOS occupying 0.0099 mm2. The ADC shows a signal-to-noise-and-distortion ratio (SNDR) of 30.61 dB and a spurious-free dynamic range (SFDR) of 43.37 dB. It consumes 8.1 mW at Nyquist frequency with 0.9-V supply voltage. The resulting Walden figure of merit FoM $_{W}$ is 73.1-fJ/conversion-step. No more than 1.07-dB SNDR variations are obtained for supply voltage varying from 0.85 to 0.95 V.