Failure Mechanism Analysis on Single Pulse Avalanche for SiC MOSFETs

The avalanche failure mechanism of 1200 V 40-mΩ planar silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistor (MOSFET) is investigated in this article. Unclamped inductive switching (UIS) test is performed and the junction temperature is extracted by an accurate model to illustrate the relationship between failure temperature and avalanche current. The failure temperature shows little dependence on current and a critical temperature window around 980 K ~ 1100 K is found. The probability of the latch-up of parasitic bipolar junction transistor (BJT) and metal system damage is studied by an analytical model and the thermal diffusion equation. With further theoretical analysis and validation, the failure mechanism is demonstrated as the metal system damage because the high-temperature transition exceeds the sustainable time of SiC MOSFETs. TCAD simulation is also used to verify this mechanism and the temperature evolution suggests that aluminum is likely to melt during the avalanche.