The Effect of $\text{CdSe}_{\mathrm{X}}\text{Te}_{1-\mathrm{X}}$ Thickness on the $\text{CdSe}_{\mathrm{X}}\text{Te}_{1-}$ x/CdTe Solar Cell Performance

The effect of the $\mathbf{CdSe}_{\mathbf{x}}\mathbf{Te}_{\mathbf{1-x}}$ (CST) thickness on the performance of $\mathbf{CdSe}_{\mathbf{X}}\mathbf{Te}_{\mathbf{1-X}}/\mathbf{CdTe}$ solar cells at different Se (x) compositions and annealed at various $\mathbf{CdCl_{2}}$ temperatures has been studied. The cell configuration was superstrate as $\mathbf{ITO/MZO/CdSexTe_{1-X}/CdTe/Back}$ Contact. Both CST and CdTe were deposited by the close-spaced sublimation (CSS) process. The CST thickness and Se composition varied from $\boldsymbol{0.25-1\ \mu} \mathbf{m}$ and 6-29% respectively. The open circuit voltage (Voc) was found to decrease with increasing CST thickness and Se composition. Voc decreases, and $\mathbf{J}_{\mathbf{SC}}$ increases due to the decrease in the bandgap of CST. A CST thickness of $\boldsymbol{0.50\ \mu}\mathbf{m}$ produced the optimum Voc and fill factor, thus giving the optimum efficiency. Also, $\boldsymbol{430^{0}}\mathbf{C\ CdCl}_{\boldsymbol{2}}$ annealing temperature appears to result in a higher minority carrier lifetime, which is responsible for the improved cell performance observed for devices annealed at this temperature.