24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL

The sub-THz frequency range has been getting attention for next-generation communications, such as B5G and 6G. Among them, the $H-\text{band} (220 \ \text{to} \ 325\text{GHz})$ can be an attractive choice for wide data bandwidths and massive $\text{MIMO}$ . Local oscillator $(\text{LO})$ signals with low phase noise $(\text{PN})$ are essential for $H-\text{band}$ transceivers to accommodate advanced modulations, such as $M-\text{QAM}$ [1]. Unlike the $\text{GHz}$ band, due to the technology limitation making $\text{LO}$ signals is challenging to simultaneously obtain high output power $(P_{\text{out}})$ and low $\text{PN}$ , which directly affect the mixer conversion gain and receiver sensitivity. The low $P_{\text{out}}$ of $\text{LOs}$ could be resolved by adopting additional $H-\text{band}$ amplifiers. However, designing $H-\text{band}$ amplifiers with high $P_{\text{out}}$ is another challenge in given $\text{DC-power}$ and chip-area conditions. For implementing a $\text{sub-THz}$ signal source with 10w $\text{PN}$ , a frequency-stabilization technique was reported [2], but low $\text{PN}$ was not accomplished due to the extremely high operating frequency. An $H-\text{band}$ architecture using a sub-sampling $\text{PLL (SSPLL)}$ with various frequency multipliers was introduced in [3]. Although it obtained good $\text{PN}$ , it showed low $P_{\text{out}}$ Recently, [4] presented an $H- \text{band}$ signal source with high $P_{\text{out}}$ implemented in a SiGe process with large $\text{DC-power}$ and area-consumption issues.