Latency-Aware Frequency Scaling in Time-Triggered Network-on-Chip Architecture

Low power consumption is one of the major design requirements for Network-on-Chip (NoC) based multi-core architectures. Scaling the voltage and frequency of NoC during run-time allows to optimize power consumption within the chip. However, the associated latency increase and throughput degradation limit its use. Scaling the frequency of routers can affect the performance of the NoC, as the frequency of routers may be scaled down while they are still active. On the other hand, using time-triggered communication in the NoC ensures predictability and deterministic communication and facilitates frequency scaling at the router level according to a predefined schedule. Consequently, the time-triggered scaling of router frequency optimizes the power consumption of the NoC. It also preserves the performance of the NoC by adjusting the frequency of routers at a specific time defined by the schedule and guaranteeing that each router's frequency is clock-gated only when it is idle. This article discusses about the architecture of a time-triggered NoC equipped with power-saving techniques that enable frequency scaling of the NoC routers while preserving the system's performance and predictability.