Fast-transient Capacitor-Less LDO in 0.18µm SOI Technology

Based on 0.18µm SOI process, a fast transient capacitor-less is designed. An LDO with 1.6-2.3 voltage input range, 0-100mA load and 1.5V output voltage is designed. The circuit includes a bandgap reference circuit, a folded structure error amplifier, a super-gm source follower, an active capacitor circuit and an output power stage. Simulation results show that the proposed LDO is stable over the full load range, with a worst-case loop gain of 85dB, PM of 87deg, and GBW>100kHz. This design achieves a load regulation of $\boldsymbol{3\mu}\mathbf{V}/\mathbf{mA}$ , a linear regulation of 9mV/V and a PSR of -33dB. The transient simulation results show that the load jumps from 0 to 100mA in $\boldsymbol{1\mu}\mathbf{s}$ , the overshoot voltage is 57mV, the undershoot voltage is 112mV, and the settling time is $< \boldsymbol{1.5\mu} \mathrm{s}$ . The quiescent current is $\boldsymbol{32\mu}\mathbf{A}$ when the LDO is on, and 630nA when the LDO is off. The temperature characteristic of this circuit is 8ppm/°C, and the circuit layout area is 0.063mm ² .