Synchronization Design Method for High-Speed Signal Transmission Between FPGAs in DIGITAL Oscilloscope

Ultra-high-speed data acquisition systems generally adopt a “master-slave“ FPGA control architecture. Under this architecture, the synchronous transmission of signals between multiple FPGAs is an important prerequisite for realizing the synchronization and accurate acquisition of the acquisition system. This paper focuses on the problem of synchronous signal transmission between multiple FPGA boards and proposes a method for synchronous transmission of high-speed signals between FPGAs. With the help of the IODELAY unit of the FPGA, the most stable synchronous transmission interval is found through the test data training, and the L VDS and SERDES synchronous transmission of multiple lanes between multiple FPGAs is realized. Experiments on a self-made digital oscilloscope show that this method can effectively realize the synchronous transmission of high-speed signals between FPGAs.