ReMCOO: An Efficient Representation of Sparse Matrix-Vector Multiplication

Sparse matrix-vector (SpMV) multiplication is the computationally intensive operation used in applications such as image classification, image recognition, circuit simulation, forecasting, etc. Different design efforts have been made to implement $S$ pMV multiplications in the FPGA platforms. The existing design approaches for $S$ pMV multiplications directly rely on the sparse matrix representations resulting in architectures for $S$ pMV multiplications with high resource count and latency. Implementing $S$ pMV multiplications with minimal latency and hardware resources remains an open problem. In this paper, we address this problem. More precisely, we propose a sparse matrix-vector representation called Redundant Modified Coordinate (ReMCOO) form to implement the sparse matrix-vector multiplications. The FPGA implementations show that our proposed approach based on the new representation ReMCOO can result in average reductions of up to 67%, 96%, and 25.71% in LUT count, FF count, and latency, respectively with an average increase of up to 20% in on-chip memory size. The experimental results confirm the effectiveness of the proposed $S$ pMV representation over the existing ones.