GRASP-based High-Level Synthesis Design Space Exploration for FPGAs

High-Level Synthesis (HLS) provides substantial productivity gains for the development of dedicated accelerators, including those based on FPGAs. Attaining efficient designs in terms of important design metrics such as resource use and performance, however, usually requires manually introducing synthesis optimization directives to properly steer the synthesis process, which creates the need for long optimization cycles and compromises the productivity gains. Thus, Design Space Exploration (DSE) heuristics have been proposed to automate and accelerate this process. In this work, we propose a novel DSE heuristic for FPGA-oriented HLS, based on Generic Randomized Adaptive Search Procedures (GRASP). We demonstrate its effectiveness compared to other heuristics previously employed for this problem. Moreover, we have developed all evaluated heuristics on an open-source and extensible DSE framework that fosters reproducible and comparable future research on the area. We show that the GRASP-based DSE is able to reduce the average distance from reference set by nearly 50% and to improve Pareto dominance by 19% when compared to previous DSE approaches.