Myrmec: FPGA-Accelerated SmartNIC for Cost and Power Efficient IoT Sensor Networks.

Battery-powered wireless sensor nodes are one of the fundamental components of IoT-style wide-scale data collection and processing, but their capabilities are often restricted by the limited wireless transmission bandwidth achievable under the stringent power envelope imposed by the battery or power harvesters. Extreme edge computing attempts to mitigate this issue by offloading some computation to the sensor nodes with the aim of reducing the wireless data transfer requirements, and it has shown great promise especially using application-specific hardware acceleration on reconfigurable fabrics such as FPGAs. However, simply attaching an FPGA accelerator as a peripheral to the embedded microcontroller requires microcontroller software to move data between the accelerator and network interface, which can quickly become the bottleneck for high-speed data collection and processing. In this work, we present Myrmec, a SmartNIC architecture which mitigates this burden by placing a low-power FPGA on the datapath between the microcontroller and NIC. We present a carefully optimized architecture for wireless data collection, and use three important application scenarios to show that it can improve effective bandwidth by up to almost 3 × compared to a standalone accelerator, which is on top of the order of magnitude reduction in wireless data transfer thanks to extreme edge computing. Thanks to reduction of wireless data transfer, Myrmec can reduce the overall power consumption of the node, despite the addition of acceleration which significantly improves data collection performance.