Board level FEA reliability and stress modeling for chip-to-wafer bonded chiplet package

Chip-to-wafer interconnect approach is to produce denser and smaller dies, while improving inter-chip bandwidth and power dissipation. In this work a vertical system integration is done by copper pillar and solder interconnects. Three-dimensional (3D) integration technology uses chip-to-wafer bonding to achieve effective chip integration. By structural simulation and modeling a reliable package selection is made from different package designs, epoxy mold compounds (EMC), polymer dielectric (PD) materials and different other package parameters. In this simulation and modeling an approach has been taken to model two levels of solder interconnects namely copper pillar solder micro-bump and BGA (ball grid array) solder in the same FEA (finite element analysis) model. FEA mesh densities in 1st and 2nd interconnects are joined by contact pair definition. Parametric studies are done for three different EMC and three different PD materials. 1st level solder interconnect or micro-bump temperature cycling (TC) reliability life is significantly higher than 2nd level solder interconnect due to presence of EMC around the 1st level interconnect. High CTE (coefficient of thermal expansion) of EMC shows very poor solder life for 1st level solder interconnect. PD material CTE shows significant impact on component side solder life for 2nd level interconnect. Also, higher PD material CTE shows worsening 1st level interconnect life. Stress analysis shows pad diameter smaller than UBM (under bump metallization) opening is a better design.